What you currently want is to generate a 10MHz clock perhaps that is not what you need to do to actually fix the problem. Providing a snippet of code that is useless (generates a 0 Hz clock output) and asking if it will work isn't going to get you the answer you need (how to fix your problem). not including information about the constraints of the problem being in a CPLD or even which CPLD, not including the can't change hardware, not including what the actual problem is with timing, not including why you need a reduction in clock frequency of 25 MHz down to 10 MHz. If this isn't the case then this is just another case of a newbie Edaboard member not asking a clear question or even the right question with supporting information for others to make truly helpful suggestions.Į.g. Seems to me a timing problem that requires 60ns more time is not a timing problem it's a design problem. Which becomes 100ns for the same setup constraint. Those are some pretty big timing issues!?Ģ5 MHz = 40 ns period i.e.
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